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Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
FEATURES
* 6 differential LVPECL outputs * 1 differential PCLK, nPCLK input pair * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL * Maximum output frequency: > 2GHz * Output skew: 30ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 510ps (maximum) * Jitter, RMS: < 0.03ps (typical) * LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * Lead-Free package available * -40C to 85C ambient operating temperature
GENERAL DESCRIPTION
The ICS853006 is a low skew, high performance 1-to-6 Differential-to-2.5V/3.3V LVPECL/ECL HiPerClockSTM Fanout Buffer and a member of the HiPerClock TM S family of High Performance Clock Solutions from ICS. The ICS853006 is characterized to operate from a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS853006 ideal for those applications demanding well defined performance and repeatability.
ICS
BLOCK DIAGRAM
PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5
PIN ASSIGNMENT
VCC nQ0 Q0 nQ1 Q1 nQ2 Q2 VCC PCLK nPCLK 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC Q5 nQ5 Q4 nQ4 Q3 nQ3 VCC VEE VBB
V BB
ICS853006
20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm package body G Package Top View
853006AG
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1
REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Type Description Positive supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Pulldown Non-inver ting differential LVPECL clock input. Pullup/ Inver ting differential LVPECL clock input. VCC/2 default when left floating. Pulldown Bias voltage. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 8, 13, 20 2, 3 4, 5 6, 7 9 10 11 12 14, 15 16, 17 Name VCC nQ0, Q0 nQ1, Q1 nQ2, Q2 PCLK nPCLK VBB VEE nQ3, Q3 nQ4, Q4 Power Output Output Output Input Input Output Power Output Output
18, 19 nQ5, Q5 Output Differential output pair. LVPECL interface levels. NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Input Pullup/Pulldown Resistor Test Conditions Minimum Typical 75 50 Maximum Units K K
TABLE 3. CLOCK INPUT FUNCTION TABLE
Input PCLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLK 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 LOW HIGH LOW HIGH HIGH LOW Outputs Q0:Q5 nQ0:nQ5 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -4.6V (ECL mode, VCC = 0) to the device. These ratings are stress specifi-0.5V to V + 0.5 V
CC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current VBB Sink/Source, IBB Storage Temperature, TSTG Package Thermal Impedance, JA
(Junction-to-Ambient)
0.5V to VEE - 0.5V 50mA 100mA 0.5mA -65C to 150C 73.2C/W (0 lfpm)
cations only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Operating Temperature Range, TA -40C to +85C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V; VEE = 0V
Symbol VCC IEE Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 3.3 Maximum 3.465 115 Units V mA
TABLE 4B. LVPECL DC CHARACTERISTICS, VCC = 3.3V; VEE = 0V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current PCLK Input Low Current nPCLK Min
2.175 1.405 2.075 1.43 1.86 150 1.2 800
-40C Typ
2.275 1.545
Max
2.38 1.68 2.36 1.765 1.98 1200 3.3 150
Min
2.225 1.425 2.075 1.43 1.86 150 1.2
25C Typ
2.295 1.52
Max
2.37 1.615 2.36 1.765 1.98
Min
2.295 1.44 2.075 1.43 1.86 150 1.2
85C Typ
2.33 1.535
Max
2.365 1.63 2.36 1.765 1.98
Units
V V V V V
800
1200 3.3 150
800
1200 3.3 150
mV
V A A A
-10 -150
-10 -150
-10 -150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C Min
1.375 0.605 1.275 0.63 150 1.2 800
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.5V; VEE = 0V
Symbol VOH VOL VIH VIL VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK0, nPCLK High Current Input Low Current PCLK 25C Max
1.58 0.88 1.56 0.965 1200 2.5 150 -10 -10
85C Max
1.57 0.815 1.56 0.965
Typ
1.475 0.745
Min
1.425 0.625 1.275 0.63 150 1.2
Typ
1.495 0.72
Min
1.495 0.64 1.275 0.63 150 1.2
Typ
1.53 0.735
Max
1.565 0.83
Units
V V V V
-0.83
0.965 800 1200 2.5 150
800
1200 2.5 150
mV
V A A A
-10
-150 -150 -150 nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol VOH VOL VIH VIL VBB VPP VCMR IIH IIL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Input High Voltage(Single-Ended) Input Low Voltage(Single-Ended) Output Voltage Reference; NOTE 2 Peak-to-Peak Input Voltage Input High Voltage Common Mode Range; NOTE 3, 4 Input PCLK, nPCLK High Current Input Low Current PCLK -40C Min
-1.125 -1.895 -1.225 -1.87 -1.44 150 VEE+1.2V 800
25C Max
-0.92 -1.62 -0.94 -1.535 -1.32 1200 0 150
85C Max
-0.93 -1.685 -0.94 -1.535 -1.32
Typ
-1.025 -1.755
Min
-1.075 -1.875 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-1.005 -1.78
Min
-1.005 -1.86 -1.225 -1.87 -1.44 150 VEE+1.2V
Typ
-0.97 -1.765
Max
-0.935 -1.67 -0.94 -1.535 -1.32
Units
V V V V V
800
1200 0 150
800
1200 0 150
mV
V A A A
-10
-10
-10
-150 -150 -150 nPCLK Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50 to VCC - 2V. NOTE 2: Single-ended input operation is limited. VCC 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLK, nPCLK is VCC + 0.3V.
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
-40C Min 340 Typ >2 400 15 460 27 150 0.03 95 150 205 95 0.03 150 205 95 350 Max Min 25C Typ >2 410 15 470 27 150 0.03 150 205 390 Max Min 85C Typ >2 450 17 510 30 150 Max
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -2.375V TO -3.465V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol fMAX Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time 20% to 80% Units GHz ps ps ps ps ps
tPD tsk(o) tsk(pp) tjit
tR/tF
All parameters are measured 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 155.52MHz
= 0.03ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
VCC
Qx
SCOPE
nPCLK
LVPECL
nQx PCLK
V
PP
Cross Points
V
CMR
VEE
V EE
-0.375V to -1.465V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx PART 1 Qx nQy PART 2 Qy
nQx Qx nQy Qy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nPCLK
80% Clock Outputs
80% VSW I N G
PCLK nQ0:nQ5 Q0:Q5
20% tR tF
20%
tPD
OUTPUT RISE/FALL TIME
853006AG
PROPAGATION DELAY
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows an example of the differential input that can be wired to accept single ended levels. The reference voltage level VBB generated from the device is connected to the negative input.
The C1 capacitor should be located as close as possible to the input pin.
VCC
C1 0.1u CLK_IN
PCLK VBB nPCLK
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
TERMINATION
FOR
3.3V LVPECL OUTPUTS
50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive
Zo = 50
3.3V 125 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o 50 VCC - 2V RTT
FIN
Zo = 50 84 84
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
853006AG
FIGURE 2B. LVPECL OUTPUT TERMINATION
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Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to
2.5V
2.5V 2.5V VCC=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A NOVEMBER 9, 2004
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ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK R2 50
3.3V Zo = 50 Ohm
3.3V
R1 100 Zo = 50 Ohm
PCLK nPCLK HiPerClockS PCLK/nPCLK
CML Built-In Pullup
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
R5 100 - 200 R6 100 - 200 R1 50 R2 50 Zo = 50 Ohm C2 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 PCLK VBB nPCLK PC L K/n PC LK
R4 125
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V 3.3V 2.5V R3 120 SSTL Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK HiPerClockS PCLK/nPCLK R4 120
3.3V 3.3V Zo = 50 Ohm LVDS R5 100 Zo = 50 Ohm R1 1K R2 1K C1 PCLK C2 VBB nPCLK PC L K /n PC L K
R1 120
R2 120
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
FIGURE 4F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc. SCHEMATIC EXAMPLE
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Additional LVPECL driver termination approaches are shown in the LVPECL Termination Application Note. It is recommended at least one decoupling capacitor per power pin. The decoupling capacitors should be physically located near the power pins. For ICS853006, the unused output can be left floating.
Figure 5 shows a schematic example of ICS853006. The ICS853006 input can accept various types of differential input signal. In this example, the inputs are driven by an LVPECL drivers. For the ICS853006 LVPECL output driver, an example of LVPECL driver termination approach is shown in this schematic.
Zo = 50
+
Zo = 50
-
R2 50
R1 50
3.3V
U1
ICS853006
3.3V
R3 50
C5 (Optional) 0.1u
3.3V
Zo = 50
1 2 3 4 5 6 7 8 9 10
VCC nQ0 Q0 nQ1 Q1 nQ2 Q2 VCC PCLK nPCLK
VCC Q5 nQ5 Q4 nQ4 Q3 nQ3 VCC VEE VBB
20 19 18 17 16 15 14 13 12 11
Zo = 50
+
Zo = 50
-
Zo = 50
3.3V LVPECL
R5 50
R4 50
R9 50
R10 50
(U1, 1)
3.3V
(U1, 8)
(U1, 13)
(U1, 20)
R6 50
C6 (Optional) 0.1u
C7(Optional) 0.1u
R11 50
C1 0.1u
C2 0.1u
C3 0.1u
C4 0.1u
FIGURE 5. ICS853006 LVPECL CLOCK OUTPUT BUFFER SCHEMATIC EXAMPLE
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REV. A NOVEMBER 9, 2004
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ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853006. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS853006 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 115mA = 398.48mW Power (outputs)MAX = 30.94mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.94mW = 185.64mW
Total Power_MAX (3.465V, with all outputs switching) = 398.48mW + 185.64mW = 584.12mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.584W * 66.6C/W = 123.9C. This is below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA
FOR
20-PIN TSSOP, FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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REV. A NOVEMBER 9, 2004
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3. Calculations and Equations.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50 VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V.
CC
*
For logic high, VOUT = V (V
CC_MAX
OH_MAX
=V
CC_MAX
- 0.935V
-V
OH_MAX
) = 0.935V =V - 1.67V
*
For logic low, VOUT = V (V
CC_MAX
OL_MAX
CC_MAX
-V
OL_MAX
) = 1.67V
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V - (V - 2V))/R ] * (V
L
OH_MAX
CC_MAX
CC_MAX
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
L
CC_MAX
-V
OH_MAX
)=
[(2V - 0.935V)/50] * 0.935V = 19.92mW
Pd_L = [(V
OL_MAX
- (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.67V)/50] * 1.67V = 11.02mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.94mW
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REV. A NOVEMBER 9, 2004
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ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
by Velocity (Linear Feet per Minute)
JA
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 114.5C/W 73.2C/W
200
98.0C/W 66.6C/W
500
88.0C/W 63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853006 is: 1340
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REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
20 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 Millimeters Minimum 20 1.20 0.15 1.05 0.30 0.20 6.60 Maximum
Reference Document: JEDEC Publication 95, MO-153
853006AG
www.icst.com/products/hiperclocks.html
15
REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
Marking Package 20 Lead TSSOP 20 Lead TSSOP on Tape and Reel 20 Lead "Lead-Free" TSSOP 20 Lead "Lead-Free" TSSOP on Tape and Reel Count 72 per tube 2500 72 per tube 2500 Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS853006AG ICS853006AGT ICS853006AGLF ICS853006AGLFT ICS853006AG ICS853006AG ICS853006AGL ICS853006AGL
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 853006AG
www.icst.com/products/hiperclocks.html
16
REV. A NOVEMBER 9, 2004
Integrated Circuit Systems, Inc.
ICS853006
LOW SKEW, 1-TO-6 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
REVISION HISTORY SHEET Description of Change Added Lead-Free bullet to Features section. Added Lead-Free P/N to Ordering Information table. Date 11/9/04
Rev A
Table T8
Page 1 16
853006AG
www.icst.com/products/hiperclocks.html
17
REV. A NOVEMBER 9, 2004

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